Summary: This session introduces Ultra-Precision Deposition (UPD) as a unique additive manufacturing solution for the single-step filling of vertical interconnects in silicon and glass. The presentation demonstrates how direct-write technology simplifies 3D microelectronic packaging by bypassing complex conventional metallization steps.
Full
Description: As 3D integrated circuits (3D ICs) advance, conventional metallization processes often struggle with high complexity and limited flexibility. This presentation explores Ultra-Precision Deposition (UPD), a high-resolution digital printing method, as a pivotal alternative for fabricating Through-Silicon Vias (TSVs) and Through-Glass Vias (TGVs).
The session details the application of UPD using specialized silver nanoparticle pastes across silicon and glass platforms. Results showcase exceptional aspect ratios, reaching up to 14:1 on silicon and 10:1 on glass. Unlike traditional workflows, the UPD method enables uniform filling and contact bump integration in a single, continuous process.
The discussion covers morphological findings via SEM-PFIB analysis, specifically addressing how CTE mismatch and volatile evaporation impact post-sintering stability. The presenter explains how custom R&D pastes with specific rheological profiles mitigated internal voiding and improved adhesion. Finally, electrical data confirms functional continuity with low measured resistances establishing UPD as a versatile platform for flexible back-end-of-line integration.
Adoption Stage: Evaluation
Learning Objectives:
Upon completion, participants will be able to evaluate the capability of Ultra-Precision Deposition (UPD) technology to achieve high-resolution, high-aspect-ratio (up to 14:1) filling of vertical vias across heterogeneous substrates.
Upon completion, participants will be able to analyze the thermomechanical challenges (CTE mismatch) driving deformation and void formation in confined silver paste TSV structures.
Upon completion, participants will be able to analyze the relationship between UPD's process control and the final electrical performance, confirming the viability of the technique for reliable 3D microelectronic integration.
